1. Field of the Invention
The present invention broadly relates to the field of the integrated circuit memories, especially in EEPROM technology (electrically erasable and programmable read only memory) and more particularly the present invention related to address registers for addressing cells in serial access memories.
2. Description of Related Art
The architecture of a prior art serial access memory as known in the state of the art is shown schematically in FIG. 1.
The memory first of all comprises what is known as a memory space MM. The memory space is formed by a matrix of memory cells fabricated according to a given technology. A memory cell memorizes the value of one bit of the memory. The cells of a same column are connected to a same connection line, classically depicted vertically and referred to as the bit line. In addition, cells of a same line are connected to a same connection line, classically depicted horizontally and referred to as a word line. As uses herein through out the following sections, the term "word lines" and "bit lines" are designated by the generic expression "access line".
To access a cell (e.g., for a read or write operation) it is necessary to activate the bit line and the word line to which the cell is connected. The term "activate" is herein understood as the action of bringing the access line under consideration to a determined voltage potential (which is a function of the read or write operation to carry out). The action of activating a given one of the access lines belonging to a same group (of bit lines or word lines), and that one access line only, is herein referred to as "selecting the access line." This access line selection is carried out by a decoder circuit, more simply known as a line access decoder. The memory thus comprises a word line decoder ROWDEC and a bit line decoder COLDEC.
The memory also comprises a set of column registers LAT cooperating with the bit line decoder to activate the bit lines.
For writing or reading a binary word in the memory, an instruction is received at a serial data input DI of the memory, according to a determined serial data transmission protocol (for example the I.sup.2 C, SPI or MICROWIRE protocols). Since the binary data of the instruction are sent to the input DI in the form of an electrical signal, thee binary data is typically reshaped by an input buffer INBUF. It is important to note, that the INBUF circuit is not manditory and can be omitted in certain applications. In general, the following information is contained in the instruction: operation code (e.g.: writing or reading), a memory address designating a memory word, and, as the case arises, at least one word of data to be written (for a writing operation). A sequencer SEQ generates command signals for the proper operation of the memory during execution of a received instruction. The sequencer SEQ receives a clock signal CLK via a clock input CK of the memory. The command signals it generates are depicted by arrows in broken lines.
Thus, the data corresponding to the address of the memory word concerned by the operation are loaded in a shift register or an address register AREG under command of the sequencer SEQ. From there, an address bus ADDRES_BUS sends a first part x.sub.i of the memory word address, referred to as the column address, up to a bit line decoder COLDEC, and another part y.sub.j of the memory word address, referred to as the line address, up to a word decoder RODEC. In the example depicted in FIG. 1, the complete address of one memory word is coded on 8 bits whereupon the address bus ADDRESS_BUS comprises eight transmission lines. The address is then divided into two parts x.sub.i and y.sub.j each of four bits, whereupon the address bus ADDRESS_BUS splits into two parts each of four transmission lines. The address register AREG is then an 8-bit register, i.e., it comprises a plurality of memory latches (or flip-flops) in series, respectively for storing the eight consecutively received address bits. It provides the function of effecting a serial-to-parallel conversion of the flow of address bits received by the memory via input DI. To this end, an output of each of the eight latches of the register AREG is respectively connected to one of the eight transmission lines of the address bus ADDRESS_BUS.
Likewise, the instruction data corresponding to a word to be written (as the case arises) are loaded into an input shift register DREG under control of the sequencer SEQ. The register DREG is an 8-bit register, i.e. it comprises eight memory latches in series respectively for storing the eight consecutively received data bits. The shift register DREG provides a series-to-parallel conversion of the flow of data bits received by the memory via the serial data input DI. As a result, an output of each of the eight latches of register DREG is respectively connected to one of the eight transmission lines of a data input bus INPUT_DATA_BUS. Bus INPUT_DATA_BUS is moreover connected to the set column registers LAT to supply the latter with eight data bits in parallel form. These binary data are loaded into storage and switching latches of the column register associated with the memory word concerned, under control of sequencer SEQ.
One shortcoming of the prior art serial access memories is that the address register AREG takes up a lot of space on the doped silicon substrate on which the memory is formed. This is due to the large number of transistors that compose the memory. It is important to point out that the dope silcon area occupied by the shift register is penalizing in terms of fabrication cost, especially for low capacity memories storing only a few bytes.
Accordlying, a need exists for a method and a system and to overcome the shortcoming of the use of AREG address registers for address memory circuits.